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W155
Spread Spectrum Frequency Timing Generator
Features
* Generates a spread spectrum timing signal (SYSCLK) and a non-spread signal (USBCLK) * Requires a 14.318-MHz crystal for operation * Supports MIPS microprocessor clock frequencies * Reduces peak EMI by as much as 12 dB * Integrated loop filter components * Cycle-to-cycle jitter = 250 ps (max) * Operates with a 3.3 or 5.0V power supply * Spread output is selectable from 10 to 133 MHz * TEST mode supports modulation off (High-Z) and special test input reference frequency * Guaranteed 45/55 duty cycle * Packaged in a 16-pin, 300-mil-wide SOIC (Small Outline Integrated Circuit) Table 1. Frequency Selection (14.318-MHz Reference) FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SYSCLK (Output Freq.) 133.3 MHz 120 MHz 100 MHz 74.77 MHz 70 MHz 66.6 MHz 60 MHz 50 MHz 40 MHz 33.33 MHz 30 MHz 25 MHz 20 MHz 16.67 MHz 12 MHz 10 MHz
Overview
The W155 incorporates the latest advances in PLL-based spread spectrum frequency synthesizer technology. By frequency modulating the SYSCLK output with a low-frequency carrier, peak EMI can be greatly reduced in a system. Use of this technique allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system that uses the W155, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to SYSCLK. Therefore, the benefits of using this technique increase with the number of address and data lines in the system. The W155 is specifically targeted toward MIPS microprocessor based systems where EMI is of particular concern. Each device uses a single 14.318-MHz crystal to generate a selectable spread spectrum output and an unmodulated 48-MHz USB Output. The spreading function can be disabled by taking the SSON# pin high. Spread percentage can be selected with the SS% input (see Table 2 below).
Table 2. Spread Percentage Selection SS% 0 1
[1]
Spread Percentage -1.25% -3.75%
Pin Configuration
VDD X1 X2 GND FS3* VDD FS2* FS1* 1 2
16 15 W155 14 13 12 11 10 9
TEST VDD USBCLK/SS%* GND SYSCLK GND FS0* SSON#^
3 4 5 6 7 8
Note: 1. Internal pull-up resistor present on inputs marked with `*' and pull-down resistor present on input marked with `^'.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 September 29, 1999, rev. **
W155
Pin Definitions
Pin Name USBCLK/ SS% Pin No. 14 Pin Type I/O Pin Description USB Clock Output/Modulation Width Selection Input: When an input; if spread spectrum feature is enabled, this pin is used to select the amount of frequency variation on the SYSCLK output (see Table 2). Wider variations result in greater peak EMI reduction. When an output: supplies a non-spread 48-MHz signal for USB support. System Clock Output: Frequency is selected per Table 1. Spread spectrum feature is controlled by pins 9 & 14. Frequency Select Pins: These pins set the frequency of the signal provided at the SYSCLK output. Spread Spectrum Control (active LOW): Pulling this input signal HIGH turns the internal modulating waveform off. This pin has an internal pull-down resistor. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as either an external crystal connection, or as an external reference frequency input. Crystal Connection: If using an external reference, this pin must be left unconnected. Test Mode: For normal operation, tie this pin to ground. Power Connection: Connected to either 3.3V or 5.0V power supply. All VDD pins must be the same voltage level. Ground Connection: Connect to the common system ground plane.
SYSCLK FS0:3 SSON# X1
12 10, 8, 7, 5 9 2
O I I I
X2 TEST VDD GND
3 16 1, 6, 15 4, 11, 13
I I P G
2
W155
Functional Description
I/O Pin Operation Pin 14 is a dual purpose l/O pin. Upon power-up each I/O pin acts as a logic input, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and each pin then becomes a clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between each l/O pin and ground or VDD. Connection to ground sets a "0" bit, connection to V DD sets a "1" bit. See Figure 1. Upon W155 power-up, the first 2 ms of operation is used for input logic selection. During this period, each clock output buffer is three-stated, allowing the output strapping resistor on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O pin is then latched. Next the output buffer is enabled converting all l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock outputs is <40 (nominal) which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When each clock output is enabled following the 2-ms input period, target (normal) output frequency is delivered assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The device outputs are CMOS-type which provide rail-to-rail output swing. Crystal Oscillator The device requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The input threshold voltage of pin X1 is (VDD)/2. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The device incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 20 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 20 pF should be used. This will typically yield reference frequency accuracies within 100 ppm. To achieve similar accuracies with a crystal calling for a greater load, external capacitors must be added such that the total load (internal, external, and parasitic capacitors) equals that called for by the crystal.
Jumper Options
VDD 10 k W155 Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Output Strapping Resistor Series Termination Resistor R Clock Load
Q
Data Latch
Figure 1. Input Logic Selection Through Jumper Option
3
W155
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 2. As shown in Figure 2, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 3. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is specified in Table 2. Figure 3 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for pin 9.
EMI Reduction
Spread Spectrum Enabled NonSpread Spectrum
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN
Figure 3. Typical Modulation Profile
4
100%
W155
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 Unit V C C C
Parameter VDD, VIN TSTG TA TB
Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias
DC Electrical Characteristics: 0C < TA < 70C, VDD = 3.30V10%
Parameter IDD VIL VIH VOL VOH IOL IOH IIL IIH CI CL Description Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Input Low Current Input High Current Input Capacitance XTAL Load Capacitance 5 20 IOL = 2 mA IOH = -2 mA VOL = 1.5V VOH = 1.5V 3.10 80 80 110 120 155 175 10 10 10 2.0 50 Test Condition Min Typ Max 35 0.8 Unit mA V V mV V mA mA A A pF pF
Switching Characteristics
Parameter tTLH, tTHL tTLH, tTHL tSYM tJCC EMI Description Output Rise and Fall Time measured at 10% of 90% of VDD Output Rise and Fall Time measured at 0.8V-2.0V Output Duty Cycle Cycle-to-Cycle Jitter EMI Attenuation 11th Harmonic, 25 MHz 10 Test Conditions Min 0.8 0.3 45 Typ Max 4.0 1.0 55 250 Unit ns ns % ps dB
Ordering Information
Ordering Code W155 Document #: 38-00785 Package Name G Package Type 16-pin Plastic SOIC (300-mil, wide body)
5
W155
Package Diagram
16-Pin Small Outlined Integrated Circuit (SOIC, 300 mils, wide body)
1
16 0.009 - 0.0125 (0.23 - 0.32)
0.399 - 0.412 (10.13 - 10.46)
5Nom
0.024 - 0.040 (0.61 - 1.02) 8 9
0.285 - 0.299 (7.42 - 7.59) 0.40 - 0.41 (10.16 - 10.41)
0.189 - 0.196 (4.80 - 4.98) 0.097 - 0.104 (2.46 - 2.64)
0.014 - 0.019 (0.35 - 0.48)
0.05 (1.27) BSC
0.0020 - 0.015 (0.06 - 0.38)
Note: All linear dimensions are in inches and parenthetically in millimeters, min. - max.
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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